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LTM9004 1 9004f v cc1 = 5v v cc3 = 3v v cc2 v dd lna 0 90 i q lo 2 dc offset control LTM9004-ad gnd ognd 9004 ta01 dac of adc mux adc clk clkout ov dd 0.5v to 3.6v offset adjust adc typical application description 14-bit direct conversion receiver subsystem the ltm ? 9004 is a 14-bit direct conversion receiver subsystem. utilizing an integrated system in a package (sip) technology, the LTM9004 is a module ? receiver that includes a dual high speed 14-bit a/d converter, lowpass flter, differential gain stages and a quadrature demodulator. contact linear technology regarding customization. the LTM9004 is perfect for zero-if communications applications, with ac performance that includes 76db snr and 63.5db spurious free dynamic range (sfdr). the entire chain is dc-coupled and provides access for dc offset adjustment. the integrated on-chip broadband transformers provide 50 single-ended interfaces at the rf and lo inputs. a 5v supply powers the mixer and frst amplifer for minimal distortion while a 3v supply allows low power adc operation. a separate supply allows the outputs to drive 0.5v to 3.3v logic. an optional multiplexer allows both channels to share a digital output bus. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. features applications n integrated dual 14-bit, high-speed adc, lowpass filter, differential gain stages and i/q demodulator n lowpass filter for each adc channel 1.92mhz (LTM9004-aa) 4.42mhz (LTM9004-ab) 9.42mhz (LTM9004-ac) 20mhz (LTM9004-ad) n rf input frequency range: 0.7ghz to 2.7ghz n 50 single-ended rf and lo ports n i/q gain mismatch: 0.2db typical n i/q phase mismatch: 1.5 deg typical n voltage-adjustable demodulator dc offsets n 76db/1.92mhz snr (LTM9004-aa) n 63.5db sfdr (LTM9004-aa) n clock duty cycle stabilizer n low power: 1.83w n shutdown and nap modes n 15mm 22mm lga package n telecommunications n direct conversion receivers n cellular basestations LTM9004-aa: 64k point fft f in = 1950.5mhz, C1dbfs sense = v dd l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. module is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. frequency (mhz) 0 amplitude (dbfs) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 20 9004 ta01b ?100 ?120 4 8 16 12 0 ?110 hd2 hd3
LTM9004 2 9004f pin configuration absolute maximum ratings supply voltage (v cc1 , v cc2 ) ...................... C0.3v to 5.5v supply voltage (v cc3 , LTM9004-aa, LTM9004-ab) ............................................ C0.3v to 5.5v supply voltage (v cc3 , LTM9004-ac, LTM9004-ad) ............................................ C0.3v to 3.5v supply voltage (v dd , ov dd ) ...................... C0.3v to 4.0v digital output ground voltage (ognd) ........ C0.3v to 1v lo input power .................................................... 10dbm rf input power .................................................... 20dbm rf input dc voltage ............................................... 0.1v lo input dc voltage .............................................. 0.1v x_adj input voltage ........................ C0.3v to v cc1 , v cc2 sense input voltage .................................. C0.3v to v dd digital input voltage (mixenable) ............................... C0.3v to (v cc1 + 0.3v) digital input voltage (amp1enable) ........................... C0.3v to (v cc2 + 0.3v) digital input voltage (amp2enable) ........................... C0.3v to (v cc3 + 0.3v) digital input voltage (except mixenable and ampxenable) .............................. C0.3v to (v dd + 0.3v) digital output voltage ................ C0.3v to (ov dd + 0.3v) operating temperature range LTM9004c ................................................ 0c to 70c LTM9004i ............................................. C40c to 85c storage temperature range ................... C65c to 125c (notes 1, 2) order information lga package 204-lead (22mm 15mm 2.82mm) t jmax = 125c, ja = 18.2c/w, jctop = 9.9c/w, jcbottom = 6.9c/w, jb = 7.1c/w, values determined per jedec 51-9, 51-12, weight = 1.9g 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 l k j h g f e d c b m a lead free finish tray part marking* package description temperature range LTM9004cv-aa#pbf LTM9004cv-aa#pbf LTM9004v aa 204-lead (15mm 22mm 2.8mm) lga 0c to 70c LTM9004iv-aa#pbf LTM9004iv-aa#pbf LTM9004v aa 204-lead (15mm 22mm 2.8mm) lga C40c to 85c LTM9004cv-ab#pbf LTM9004cv-ab#pbf LTM9004v ab 204-lead (15mm 22mm 2.8mm) lga 0c to 70c LTM9004iv-ab#pbf LTM9004iv-ab#pbf LTM9004v ab 204-lead (15mm 22mm 2.8mm) lga C40c to 85c LTM9004cv-ac#pbf LTM9004cv-ac#pbf LTM9004v ac 204-lead (15mm 22mm 2.8mm) lga 0c to 70c LTM9004iv-ac#pbf LTM9004iv-ac#pbf LTM9004v ac 204-lead (15mm 22mm 2.8mm) lga C40c to 85c LTM9004cv-ad#pbf LTM9004cv-ad#pbf LTM9004v ad 204-lead (15mm 22mm 2.8mm) lga 0c to 70c LTM9004iv-ad#pbf LTM9004iv-ad#pbf LTM9004v ad 204-lead (15mm 22mm 2.8mm) lga C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ caution: this part is sensitive to electrostatic discharge (esd). it is very important that proper esd precautions be observed when handling the rf and lo inputs of the LTM9004.
LTM9004 3 9004f electrical characteristics symbol parameter conditions min typ max units rf input frequency range no external matching (high band) with external matching (low band, mid band) 1.5 to 2.7 0.7 to 1.5 ghz ghz lo input frequency range no external matching (high band) with external matching (low band, mid band) 1.5 to 2.7 0.7 to 1.5 ghz ghz baseband frequency range LTM9004-aa LTM9004-ab LTM9004-ac LTM9004-ad dc to 1.92 dc to 4.42 dc to 9.42 dc to 20 mhz mhz mhz mhz rf input return loss z 0 = 50, 1.5ghz to 2.7ghz, internally matched >10 db lo input return loss z 0 = 50, 1.5ghz to 2.7ghz, internally matched >10 db rf input power for C1dbfs rf = 1950mhz C7.3 dbm lo input power C13 to 5 dbm i/q gain mismatch 0.2 db i/q phase mismatch 1.5 deg lo to rf leakage rf = 900mhz rf = 1900mhz C60.8 C64.6 dbm dbm rf to lo isolation rf = 900mhz rf = 1900mhz 59.7 57.1 db db maximum dc offset voltage, no rf (note 5) 35 mv dc offset variation C40c to 85c 210 v/c gain flatness dc to 1.92mhz (LTM9004-aa) dc to 4.42mhz (LTM9004-ab) dc to 9.42mhz (LTM9004-ac) dc to 20mhz (LTM9004-ad) 0.2 0.2 0.2 0.3 db db db db group delay flatness dc to 1.92mhz (LTM9004-aa) dc to 4.42mhz (LTM9004-ab) dc to 9.42mhz (LTM9004-ac) dc to 20mhz (LTM9004-ad) 15 15 15 5 nsec nsec nsec nsec rejection LTM9004-aa 5mhz 10mhz 5.3 33.5 db db LTM9004-ab 7.5mhz 12.5mhz 1 11 db db LTM9004-ac 12.5mhz 17.5mhz 0.5 1 db db LTM9004-ad 30mhz 40mhz 1.5 5.5 db db f lpf lowpass filter cutoff frequency 1db point (LTM9004-aa) 1db point (LTM9004-ab) 1db point (LTM9004-ac) 1db point (LTM9004-ad) 4 6.3 15 28 mhz mhz mhz mhz the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. unless otherwise noted, v cc1 = v cc2 = 5v, v dd = ov dd = 3v, v cc3 = 3v (LTM9004-ac, LTM9004-ad), v cc3 = 5v (LTM9004-aa, LTM9004-ab), p lo = 0dbm. (note 3)
LTM9004 4 9004f dynamic accuracy symbol parameter conditions min typ max units iip3 input 3rd-order intercept, 1 tone 22 dbm iip2 input 2nd-order intercept, 1 tone 58 dbm snr signal-to-noise ratio at C1dbfs 1.92mhz (LTM9004-aa) 4.42mhz (LTM9004-ab) 9.42mhz (LTM9004-ac) 20mhz (LTM9004-ad) l l l l 70.6 69.7 70.3 66.3 76.1 75.2 72 68.9 db/1.92mhz db/4.42mhz db/9.42mhz db/20mhz sfdr spurious free dynamic range 2nd or 3rd harmonic at C1dbfs LTM9004-aa rf = 1950.5mhz, lo =1950mhz l 50 63.5 db LTM9004-ab rf = 1951mhz, lo =1950mhz l 50 65 db LTM9004-ac rf = 1952.5mhz, lo =1950mhz l 52.5 66 db LTM9004-ad rf = 1955mhz, lo =1950mhz l 55 64 db sfdr spurious free dynamic range 4th or higher at C1dbfs LTM9004-aa rf = 1950.5mhz, lo =1950mhz l 65 88 db LTM9004-ab rf = 1951mhz, lo =1950mhz l 70 91 db LTM9004-ac rf = 1952.5mhz, lo =1950mhz l 70 89 db LTM9004-ad rf = 1955mhz, lo =1950mhz l 70 89 db s/(n+d) signal-to-noise plus distortion ratio at C1dbfs LTM9004-aa rf = 1950.5mhz, lo =1950mhz l 51.5 58.5 db LTM9004-ab rf = 1951mhz, lo =1950mhz l 51.5 60 db LTM9004-ac rf = 1952.5mhz, lo =1950mhz l 53 61 db LTM9004-ad rf = 1955mhz, lo =1950mhz l 53 60 db hd2 2nd order harmonic distortion ratio at C1dbfs LTM9004-aa rf = 1950.5mhz, lo =1950mhz 64 db LTM9004-ab rf = 1951mhz, lo =1950mhz 66 db LTM9004-ac rf = 1952.5mhz, lo =1950mhz 66 db LTM9004-ad rf = 1955mhz, lo =1950mhz 64 db hd3 3rd order harmonic distortion ratio at C1dbfs LTM9004-aa rf = 1950.5mhz, lo =1950mhz 69 db LTM9004-ab rf = 1951mhz, lo =1950mhz 66 db LTM9004-ac rf = 1952.5mhz, lo =1950mhz 67 db LTM9004-ad rf = 1955mhz, lo =1950mhz 67 db the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. unless otherwise noted, v cc1 = v cc2 = 5v, v dd = ov dd = 3v, v cc3 = 3v (LTM9004-ac, LTM9004-ad), v cc3 = 5v (LTM9004-aa, LTM9004-ab), p lo = 0dbm.
LTM9004 5 9004f converter characteristics symbol parameter conditions min typ max units resolution (no missing codes) l 14 bits integral linearity error (note 4) differential analog input 1.5 lsb differential linearity error differential analog input 1 lsb the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. unless otherwise noted, v cc1 = v cc2 = 5v, v dd = ov dd = 3v. v cc3 = 3v (LTM9004-ac, LTM9004-ad), v cc3 = 5v (LTM9004-aa, LTM9004-ab) digital inputs and outputs symbol parameter conditions min typ max units mixer logic input (mixenable) v ih high level input voltage v cc1 = 5v l 2 v v il low level input voltage v cc1 = 5v l 1 v i in input current v in = v cc1 120 a turn on time 120 ns turn off time 750 ns first amplifer logic input (amp1enable) v ih high level input voltage v cc2 = 5v l 2.55 2 v v il low level input voltage v cc2 = 5v l 1.8 1.25 v r in input pull-up resistance v cc2 = 5v, v amp1enable = 0v to 0.5v 25 70 k turn on time 200 ns turn off time 50 ns second amplifer logic input (amp2enable, LTM9004-aa, LTM9004-ab) v ih high level input voltage v cc3 = 5v l v cc3 C 0.6 v v il low level input voltage v cc3 = 5v l v cc3 C 2.1 v r in input pull-up resistance v cc3 = 5v, v amp2enable = 2.9v to 0v 40 66 90 k turn on time 4 s turn off time 350 ns second amplifer logic input (amp2enable, LTM9004-ac, LTM9004-ad) v ih high level input voltage v cc3 = 3v l 2.55 2.25 v v il low level input voltage v cc3 = 3v l 0.7 0.4 v r in input pull-up resistance v cc3 = 3v, v amp2enable = 0v to 0.5v 60 100 140 k turn on time 200 ns turn off time 50 ns adc logic inputs (clk, oe , adcshdn, mode, mux) v ih high level input voltage v dd = 3v l 2 v v il low level input voltage v dd = 3v l 0.8 v i in input current v in = 0v to v dd l C10 10 a c in input capacitance (note 6) 3 pf i sense sense input leakage 0v < sense < 1v l C3 3 a i mode mode input leakage 0v < mode < v dd l C3 3 a the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. unless otherwise noted, v cc1 = v cc2 = 5v, v dd = ov dd = 3v. v cc3 = 3v (LTM9004-ac, LTM9004-ad), v cc3 = 5v (LTM9004-aa, LTM9004-ab)
LTM9004 6 9004f digital inputs and outputs power requirements symbol parameter conditions min typ max units v cc1 mixer supply voltage l 4.5 5.25 v v cc2 first amplifer supply voltage l 4.5 5.25 v v cc3 second amplifer supply voltage LTM9004-aa, LTM9004-ab LTM9004-ac, LTM9004-ad l l 4.5 2.7 3 5.25 3.5 v v v dd adc analog supply voltage l 2.7 3 3.6 v ov dd adc digital output supply voltage l 0.5 3 3.6 v i cc1 mixer supply current l 129 180 ma i cc1(shdn) mixer shutdown current mixenable = 0v, ampxenable = high, adcshdn = 0v, oe = 0v l 10 11 ma i cc2 first amplifer supply current l 52 63 ma i cc2(shdn) first amplifer shutdown current mixenable = 5v, amp1enable = 0v, amp2enable = high, adcshdn = 0v, oe = 0v l 7.5 9 ma i cc3 second amplifer supply current LTM9004-aa, LTM9004-ab l 21 24 ma i cc3(shdn) second amplifer shutdown current LTM9004-aa, LTM9004-ab, mixenable = amp1enable = 5v, amp2enable = 0v, adcshdn = 0v, oe = 0v l 0.8 4 ma i cc3 second amplifer supply current LTM9004-ac, LTM9004-ad l 36 44 ma i cc3(shdn) second amplifer shutdown current LTM9004-ac, LTM9004-ad, mixenable = amp1enable = 5v, amp2enable = 0v, adcshdn = 0v, oe = 0v l 0.6 4 ma i dd adc supply current l 273 306 ma the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. unless otherwise noted, v cc1 = v cc2 = 5v, v dd = ov dd = 3v. v cc3 = 3v (LTM9004-ac, LTM9004-ad), v cc3 = 5v (LTM9004-aa, LTM9004-ab) (note 3) symbol parameter conditions min typ max units logic outputs ov dd = 3v c oz hi-z output capacitance oe = 3v (note 6) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = C10a i o = C200a l 2.7 2.995 2.99 v v v ol low level output voltage i o = 10a i o = 1.6ma l 0.005 0.09 0.4 v v ov dd = 2.5v v oh high level output voltage i o = C200a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = C200a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. unless otherwise noted, v cc1 = v cc2 = 5v, v dd = ov dd = 3v. v cc3 = 3v (LTM9004-ac, LTM9004-ad), v cc3 = 5v (LTM9004-aa, LTM9004-ab)
LTM9004 7 9004f timing characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. unless otherwise noted, v cc1 = v cc2 = 5v, v dd = ov dd = 3v. v cc3 = 3v (LTM9004-ac, LTM9004-ad), v cc3 = 5v (LTM9004-aa, LTM9004-ab) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: f sample = 125mhz, clki = clkq unless otherwise noted. note 4: integral nonlinearity is defned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. the deviation is measured from the center of the quantization band. note 5: dc offset voltage is defned as the dc voltage corresponding to the output code with lo signal applied, but no rf signal. note 6: guaranteed by design, not subject to test. symbol parameter conditions min typ max units f s sampling frequency l 1 125 mhz t l clk low time duty cycle stabilizer off (note 6) duty cycle stabilizer off (note 6) l l 3.8 3 4 4 500 500 ns ns t h clk high time duty cycle stabilizer off (note 6) duty cycle stabilizer off (note 6) l l 3.8 3 4 4 500 500 ns ns t jitter sample-and-hold acquisition delay time jitter 0.2 ps rms t ap sample-and-hold aperture delay 0 ns t d clk to data delay c l = 5pf (note 6) l 1.4 2.7 5.4 ns data to clkout skew (t d - t c ) (note 6) l C0.6 0 0.6 ns t c mux to data delay c l = 5pf (note 6) l 1.4 2.7 5.4 ns data access time after oe c l = 5pf (note 6) l 4.3 10 ns bus relinquish time (note 6) l 3.3 8.5 ns pipeline latency 5 cycles symbol parameter conditions min typ max units p d(sleep) sleep power mixenable = ampxenable = 0v, adcshdn = 3v, oe = 3v, no clk 7 mw p d(nap) nap mode power mixenable = ampxenable = 0v, adcshdn = 3v, oe = 0v, no clk 33 mw p d(total) total power dissipation LTM9004-aa, LTM9004_ab, mixenable = amp1enable = amp2enable = 5v, adcshdn = 0v, f sample = max 1.83 w LTM9004-ac, LTM9004-ad mixenable = amp1enable = 5v, amp2enable = 3v, adcshdn = 0v, f sample = max 1.83 w power requirements the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. unless otherwise noted, v cc1 = v cc2 = 5v, v dd = ov dd = 3v. v cc3 = 3v (LTM9004-ac, LTM9004-ad), v cc3 = 5v (LTM9004-aa, LTM9004-ab) (note 3)
LTM9004 8 9004f 9004 td02 q + 1 q + 2 q + 4 q + 3 q di0-di13 clki = clkq = mux demodulator analog output q t d t md t ipq t h t l clkout t c dq0-dq13 i + 1 i ? 5 q ? 5 i ? 4 q ? 4 i ? 3 q ? 3 i ? 2 q ? 2 i ? 1 q ? 5 i ? 5 q ? 4 i ? 4 q ? 3 i ? 3 q ? 2 i ? 2 q ? 1 i + 2 i + 4 i + 3 i demodulator analog output i t ipi multiplexed digital output bus timing timing diagrams 9004 td01 n ? 5 n + 1 n + 2 n + 4 n + 3 n + 5 n n ? 3 n ? 4 n ? 1 n n ? 2 d0-d13, of clki = clkq analog input clkout t d t c t ap t h t l dual digital output bus timing
LTM9004 9 9004f typical performance characteristics LTM9004-aa: 64k point fft f in = 700.5mhz, C1dbfs sense = v dd LTM9004-aa: 64k point fft f in = 1950.5mhz, C1dbfs sense = v dd LTM9004-aa, baseband frequency response LTM9004-ac: 64k point fft f in = 702.5mhz, C1dbfs sense = v dd LTM9004-ac: 64k point fft f in = 1952.5mhz, C1dbfs sense = v dd LTM9004-ac, baseband frequency response LTM9004-ab: 64k point fft f in = 701.0mhz, C1dbfs sense = v dd LTM9004-ab: 64k point fft f in = 1951.0mhz, C1dbfs sense = v dd LTM9004-ab, baseband frequency response frequency (mhz) 0 amplitude (dbfs) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 20 9004 g01 ?100 ?120 4 8 16 12 0 ?110 frequency (mhz) 0 amplitude (dbfs) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 20 9004 g02 ?100 ?120 4 8 16 12 0 ?110 baseband frequency (mhz) 0 (db) ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 20 18 9004 g02a ?50 ?60 2 4 6 12 10 16 14 8 0 ?55 frequency (mhz) 0 amplitude (dbfs) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 40 9004 g03 ?100 ?120 8 16 32 24 0 ?110 frequency (mhz) 0 amplitude (dbfs) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 40 9004 g04 ?100 ?120 8 16 32 24 0 ?110 frequency (mhz) 0 amplitude (dbfs) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 60 9004 g06 ?100 ?120 10 20 40 50 30 0 ?110 baseband frequency (mhz) 0 (db) ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 80 72 9004 g06a ?50 ?60 8 16 24 48 40 64 56 32 0 ?55 frequency (mhz) 0 amplitude (dbfs) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 60 9004 g05 ?100 ?120 10 20 40 50 30 0 ?110 baseband frequency (mhz) 0 (db) ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 40 36 9004 g04a ?50 ?60 4 8 12 24 20 32 28 16 0 ?55
LTM9004 10 9004f typical performance characteristics LTM9004-ad: 64k point fft f in = 705.0mhz, C1dbfs sense = v dd LTM9004-ad: 64k point fft f in = 1955.0mhz, C1dbfs sense = v dd LTM9004-ad, baseband frequency response frequency (mhz) 0 amplitude (dbfs) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 60 9004 g08 ?100 ?120 10 20 40 50 30 0 ?110 if frequency (mhz) 0 amplitude (db) ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 160 144 9004 g09 ?50 ?60 16 32 48 96 80 128 112 64 0 ?55 frequency (mhz) 0 amplitude (dbfs) ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 60 9004 g07 ?100 ?120 10 20 40 50 30 0 ?110
LTM9004 11 9004f supply pins v cc1 (pins g5, h2), v cc2 (pins c5, c8, k5, k8): analog 5v supply for mixer and first amplifers. the specifed operating range is 4.5v to 5.25v. the voltage on this pin provides power for the mixer and amplifer stages only and is internally bypassed to gnd. v cc3 (pins c9, c12, k9, k12): analog supply for second amplifers. the specifed operating range is 4.5v to 5.5v for LTM9004-aa and LTM9004-ab. the specifed operating range is 2.7v to 3.5v for LTM9004-ac and LTM9004-ad. v cc3 is internally bypassed to gnd. v dd (pins d14, f13, g13, j14): analog 3v supply for the adc. the specifed operating range is 2.7v to 3.6v. v dd is internally bypassed to gnd. ov dd (pins d17, j17): positive supply for the digital output drivers. the specifed operating range is 0.5v to 3.6v. ov dd is internally bypassed to ognd. gnd (see table for pin locations): analog ground. ognd (pins c17, k17): digital output driver ground. analog inputs rf (pin e2): rf input pin. this is a single-ended 50 terminated input. no external matching network is required for the high frequency band. an external series capacitor (and/or shunt capacitor) may be required for impedance transformation to 50 in the low frequency band from 700mhz to 1.5ghz (see figure 4). if the rf source is not dc blocked, a series blocking capacitor should be used. otherwise, damage to the ic may result. lo (pin h3): local oscillator input pin. this is a single- ended 50 terminated input. no external matching network is required in the high frequency band. an external shunt capacitor (and/or series capacitor) may be required for impedance transformation to 50 for the low frequency band from 700mhz to 1.5ghz (see figure 6). if the lo source is not dc blocked, a series blocking capacitor must be used. otherwise, damage to the ic may result. clkq (pin g14): q-channel adc clock input. the input sample starts on the positive edge. tie clkq and clki together. clki (pin f14): i-channel adc clock input. the input sample starts on the positive edge. tie clkq and clki together. i + _adj (pin b1): dc offset adjust pin for i-channel, + line. source or sink current through this pin to trim dc offset. i C _adj (pin c1): dc offset adjust pin for i-channel, C line. source or sink current through this pin to trim dc offset. q + _adj (pin k1) : dc offset adjust pin for q-channel, + line. source or sink current through this pin to trim dc offset. q C _adj (pin l1) : dc offset adjust pin for q-channel, C line. source or sink current through this pin to trim dc offset. control pins mixenable (pin e4) : mixer enable pin. if mixenable = high (the input voltage is higher than 2.0v), the mixer is enabled. if mixenable = low (the input voltage is less than 1.0v), it is disabled. if the enable function is not needed, then this pin should be tied to v cc1 . amp1enable (pins d5, l5) : first amplifer enable pin. amp1enable = high or foating results in normal (active) operating mode for the frst amplifer in each channel. amp1enable = low (a minimum of 2.1v below v cc2 ), results in the frst amplifers being disabled. if the enable function is not needed, then this pin should be tied to v cc2 . amp2enable (pins c10, l10) : second amplifer enable pin. amp2enable = high or foating results in normal (active) operating mode for the second amplifer in each channel. amp2enable = low (a minimum of 0.45v below v cc3 ), results in the second amplifers being disabled. if the enable function is not needed, then this pin should be tied to v cc3 . adcshdnq (pin j12) : q-channel adc shutdown mode selection pin. connecting adcshdnq to gnd and oeq to gnd results in normal operation with the outputs enabled. connecting adcshdnq to gnd and oeq to v dd results in normal operation with the outputs at high impedance. connecting adcshdnq to v dd and oeq to gnd results in nap mode with the outputs at high impedance. connecting adcshdnq to v dd and oeq to v dd results in sleep mode with the outputs at high impedance. adcshdni (pin d12) : i-channel adc shutdown mode selection pin. connecting adcshdni to gnd and oei to gnd results in normal operation with the outputs enabled. connecting adcshdni to gnd and oei to v dd results in normal operation with the outputs at high impedance. pin functions
LTM9004 12 9004f pin functions connecting adcshdni to v dd and oei to gnd results in nap mode with the outputs at high impedance. connecting adcshdni to v dd and oei to v dd results in sleep mode with the outputs at high impedance. senseq (pin h13), sensei (pin e13) : adc reference pro - gramming pin. tie to v dd for normal operation. an external reference can be used, see adc reference section. mode (pin j13) : output format and clock duty cycle stabilizer selection pin. note that mode controls both channels. connecting mode to gnd selects straight binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects straight binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. mux (pin d13) : digital output multiplexer control. if mux = high, q-channel comes out on dq0 to dq13; i-channel comes out on di0 to di13. if mux = low, the output busses are swapped and q-channel comes out on di0 to di13; i-channel comes out on dq0 to dq13. to multiplex both channels onto a single output bus, connect mux, clkq and clki together. oeq (pin k13) : q-channel output enable pin. refer to adcshdnq pin function. oei (pin c13) : i-channel output enable pin. refer to adcshdni pin function. digital outputs clkout (pin e12) : adc data ready clock output. latch data on the falling edge of clkout. clkout is derived from clkq. tie clkq to clki for simultaneous operation. di0 - di13 (see table for pin locations) : i-channel (in-phase) adc digital outputs. di13 is the msb. dq0 - dq13 (see table for pin locations) : q-channel (quadrature) adc digital outputs. dq13 is the msb. of (pin h12) : overfow/underfow output. high when an overfow or underfow has occurred on either i-channel or q-channel. pin configuration a b c d e f g h j k l m 1 gnd i + _adj i C _adj gnd gnd gnd gnd gnd gnd q + _adj q C _adj gnd 2 gnd gnd gnd gnd rf gnd gnd v cc1 gnd gnd gnd gnd 3 gnd gnd gnd gnd gnd gnd gnd lo gnd gnd gnd gnd 4 gnd gnd gnd gnd mix_en gnd gnd gnd gnd gnd gnd gnd 5 gnd gnd v cc2 amp1a_ en gnd gnd v cc1 gnd gnd v cc2 amp1b_ en gnd 6 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 7 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 8 gnd gnd v cc2 gnd gnd gnd gnd gnd gnd v cc2 gnd gnd 9 gnd gnd v cc3 gnd gnd gnd gnd gnd gnd v cc3 gnd gnd 10 gnd gnd amp2a_ en gnd gnd gnd gnd gnd gnd gnd amp2b_ en gnd 11 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 12 gnd gnd v cc3 shdni clkout gnd gnd of shdnq v cc3 gnd gnd 13 di3 di0 oei mux sensei v dd v dd senseq mode oeq dq13 dq10 14 di8 di4 di1 v dd gnd clki clkq gnd v dd dq12 dq8 dq6 15 di7 di6 di2 gnd gnd gnd gnd gnd gnd dq11 dq4 dq5 16 gnd di9 di5 di10 di11 gnd gnd dq1 dq3 dq9 dq7 gnd 17 gnd gnd ognd ov dd di12 di13 dq0 dq2 ov dd ognd gnd gnd top view of lga package (looking through component)
LTM9004 13 9004f v dd ognd clkout of ov dd adc shdn refl refh mode clk mix enable v cc1 oe 9004 bd adc lpf output drivers lpf lpf rf lo adj adj sense ref buffer diff ref amp d13 d0 . . . amp2 enable v cc3 2 nd amp amp1 enable v cc2 1 st amp 1.5v reference range select block diagram figure 1. functional block diagram (only one channel is shown)
LTM9004 14 9004f operation description the LTM9004 is a direct conversion receiver targeting high linearity receiver applications, such as wireless in- frastructure with rf input frequencies up to 2.7ghz. it is an integrated module receiver utilizing system in a package (sip) technology to combine a dual, high speed 14-bit a/d converter, lowpass flters, two low noise dif - ferential amplifers per channel with fxed gain, and an i/q demodulator with dc offset adjustment. the direct conversion receiver architecture offers several advantages over the traditional superheterodyne. it eases the requirements for rf front-end bandpass fltering, as it is not susceptible to signals at the image frequency. the rf bandpass flters need only attenuate strong out-of-band signals to prevent them from overloading the front end. also, direct conversion eliminates the need for if ampli - fers and bandpass flters. instead, the rf input signal is directly converted to baseband. direct conversion does, however, come with its own set of implementation issues. since the receive lo signal is at the same frequency as the rf signal, it can easily radiate from the receive antenna and violate regulatory standards. unwanted baseband signals can also be generated by 2nd order nonlinearity of the receiver. a tone at any fre- quency entering the receiver will give rise to a dc offset in the baseband circuits. the 2nd order nonlinearity of the receiver also allows a modulated signal, even the desired signal, to generate a pseudo-random block of energy centered about dc. for this reason, the LTM9004 provides for dc offset cor- rection immediately following the i/q demodulator stage. once generated, straightforward elimination of dc offset becomes very problematic. necessary gain in the baseband amplifers increases the offset because their frequency response extends to dc. the following sections describe in further detail the op- eration of each section. the module technology allows the LTM9004 to be customized and this is described in the frst section. the outline of the remaining sections follows the basic functional elements as shown in figure 2. semi-custom options the module construction affords a new level of fexibility in application-specifc standard products. standard adc, amplifer and rf components can be integrated regardless of their process technology and matched with passive components to a particular application. the LTM9004-aa, as the frst example, is confgured with a dual 14-bit adc sampling at rates up to 125msps. the amplifers provide a total voltage gain of 14db (including the gain of the mixer). the lowpass flter limits the bandwidth to 1.92mhz. the rf and lo inputs of the i/q demodulator have integrated transformers and present 50 single-ended inputs. an external dac can be used for dc offset cancellation. however, other options are possible through linear technologys semi-custom development program. linear technology has in place a program to deliver other sample rate, resolution, gain and flter confgurations for nearly any specifed application. these semi-custom designs are based on existing components with an appropriately modifed passive network. the fnal subsystem is then tested to the exact parameters defned for the application. the fnal result is a fully integrated, accurately tested and optimized solution in the same package. for more details on the semi-custom receiver subsystem program, contact linear technology. mixer operation the rf signal is applied to the inputs of the rf transcon- ductance amplifers and is then demodulated into i/q baseband signals using quadrature lo signals which are internally generated from an external lo source by preci- sion 90 phase shifters. figure 2. basic functional elements (only half shown) 9004 f02 v dd v cc1 v cc2 v cc3 ognd gnd adc clk mixer lo rf offset adj ov dd adc lpf 2 nd amp 1 st amp
LTM9004 15 9004f broadband transformers are integrated at both the rf and lo inputs to enable single-ended rf and lo interfaces. in the high frequency band (1.5ghz to 2.7ghz), both rf and lo ports are internally matched to 50. no external matching components are needed. for the lower frequency bands (700mhz to 1.5ghz), a simple network with series and/or shunt capacitors can be used as the impedance matching network. i-channel and q-channel phase relationship the phase relationship between the i-channel output signal and the q-channel output signal is fxed. when the lo input frequency is larger (or smaller) than the rf input frequency, the q-channel outputs (dq0 to dq13) lag (or lead) the i-channel outputs (di0 to di13) by 90. dc offset adjustment each channel includes provision for adjustment of the dc offset voltage presented at the input of the a/d converter. there are two adjust terminals for each channel, so that the common mode and differential mode dc offset may be independently trimmed. these terminals are designed to accept a source or sink current of up to 0.3ma. if the currents through the two terminals are not equal, then a differential dc offset will be created. if they are equal, then the resulting dc offset will be common mode only. as an example, sinking 0.1ma from one terminal and 0.11ma from the other terminal will yield a differential dc offset of approximately 5.9mv or 48lsb. a maximum dc offset of approximately 178mv or 1457lsb can be imposed by applying a 5v differential voltage to the adjust terminals. amplifier operation each channel of the LTM9004 consists of two stages of dc-coupled, low noise and low distortion fully differential op amps/adc drivers. each stage implements a 2-pole active lowpass flter using a high speed, high performance operational amplifer and precision passive components. the cascade of two stages is designed to provide maximum gain and phase fatness, along with adjacent channel and blocker rejection. the lowpass response can be confg - ured for different cutoff frequencies within the range of the amplifers. LTM9004-aa, for example, implements a lowpass flter designed for 1.92mhz. adc input network the passive network between the second amplifer output stages and the adc input stages provides a 1st order topology confgured for lowpass response. converter operation the analog-to-digital converter (adc) shown in figure 1 is a dual cmos pipelined multistep converter. the converter has six pipelined adc stages; a sampled analog input will result in a digitized value six cycles later (see the timing diagrams section). the clk inputs are single ended. the adc has two phases of operation, determined by the state of the clk input pins. each pipelined stage contains an adc, a reconstruction dac and an interstage residue amplifer. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplifed and output by the residue amplifer. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. when clk is low, the analog input is sampled differen- tially directly onto the input sample-and-hold capacitors. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h amplifer which drives the frst pipelined adc stage. the frst stage acquires the output of the s/h during this high phase of clk. when clk goes back low, the frst stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third, fourth and ffth stages, resulting in a ffth stage residue that is sent to the sixth stage adc for fnal evaluation. each adc stage following the frst has additional range to accommodate fash and amplifer offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. operation
LTM9004 16 9004f applications information rf input figure 3 shows the mixers rf input which consists of an integrated transformer and high linearity transconduc- tance amplifers. the primary side of the transformer is connected to the rf input pin. the secondary side of the transformer is connected to the differential inputs of the transconductance amplifers. under no circumstances should an external dc voltage be applied to the rf input pin. dc current fowing into the primary side of the trans- former may cause damage to the integrated transformer. a series blocking capacitor should be used to ac-couple the rf input port to the rf signal source. at lower frequencies, however, the input return loss can be improved with the matching network shown in figure 3. shunt capacitor c10 and series capacitor c11 can be selected for optimum input impedance matching at the desired frequency as illustrated in figure 4. for lower fre - quency band operation, the external matching component c11 can serve as a series dc blocking capacitor. the rf input impedance and s11 parameters (without external matching components) are listed in table 1. table 1. rf input impedance frequency (mhz) magnitude phase () r () x () 500 0.78 C139.7 16.1 C10.7 600 0.69 C166.6 10.1 C3.8 700 0.60 163.7 14.0 3.8 800 0.52 132.6 25.8 6.9 900 0.48 102.7 41.9 3.4 1000 0.45 77.4 58.8 C4.3 1100 0.42 56.6 74.9 C11.4 1200 0.38 40.1 86.4 C12.4 1300 0.31 25.7 87.6 C7.1 1400 0.22 10.9 76.8 C1.4 1500 0.10 C14.5 60.9 0.3 1600 0.06 C132.9 45.9 C0.2 1700 0.19 C170.7 34.6 C0.4 1800 0.30 C177.7 26.8 0.2 1900 0.40 C172.1 21.8 1.1 2000 0.47 C169.4 18.7 1.9 2100 0.51 C168.6 16.7 2.2 2200 0.54 C169.3 15.4 2.3 2300 0.55 C172.0 14.7 1.7 2400 0.55 C176.0 14.4 0.9 2500 0.54 C178.7 14.9 C0.3 2600 0.52 C172.3 15.9 C1.6 2700 0.50 C164.3 17.6 C3.0 2800 0.49 C155.0 19.9 C4.3 2900 0.48 C144.7 22.9 C5.4 3000 0.48 C134.8 26.4 C6.0 lo input port the mixers lo input interface is shown in figure 5. the input consists of an integrated transformer and a preci- sion quadrature phase shifter which generates 0 and the rf input port is internally matched over a wide fre- quency range from 1.5ghz to 2.7ghz with input return loss typically better than 10db. no external matching network is needed for this frequency range. when the part is operated figure 3. rf input interface to i mixer rf external matching network for low band and mid band c10 9004 f05 c11 to q mixer rf input e2 e3 ?30 ?25 ?20 ?15 ?10 ?5 0 100 1000 10000 frequency (mhz) return loss (db) 9004 f04 no matching elements 1.95ghz match (2.7nh + 1.8pf) 700mhz match (18pf + 8.2pf) figure 4. rf port return loss vs frequency
LTM9004 17 9004f 90 phase-shifted lo signals for the lo buffer amplifers driving the i/q mixers. the primary side of the transformer is connected to the lo input pin. the secondary side of the transformer is connected to the differential inputs of the lo quadrature generator. under no circumstances should an external dc voltage be applied to the input pin. dc current fowing into the primary side of the transformer may damage the transformer. a series blocking capacitor should be used to ac-couple the lo input port to the lo signal source. the lo input impedance and s11 parameters (without external matching components) are listed in table 2. table 2. lo input impedance frequency (mhz) magnitude phase () r () x () 500 0.77 C143.2 14.8 C10.0 600 0.66 C172.6 10.6 C2.0 700 0.55 154.5 17.8 5.1 800 0.46 119.8 33.1 5.5 900 0.41 88.8 50.8 C0.3 1000 0.39 63.9 67.5 C7.4 1100 0.35 44.9 80.2 C10.1 1200 0.30 31.5 83.4 C7.2 1300 0.23 22.7 76.9 C3.1 1400 0.14 20.7 65.2 C0.9 1500 0.05 47.3 53.6 C0.1 1600 0.08 139.3 44.1 0.3 1700 0.17 152.3 36.9 0.9 1800 0.25 154.7 31.7 1.6 1900 0.31 157.5 27.9 2.0 2000 0.35 160.5 25.1 2.2 2100 0.38 164.9 23.1 2.0 2200 0.41 170.3 21.4 1.4 2300 0.42 177.7 20.2 0.4 2400 0.44 C173.8 19.6 C1.0 2500 0.46 C164.6 19.7 C2.6 2600 0.48 C155.7 20.2 C4.1 2700 0.51 C147.1 21.2 C5.6 2800 0.54 C139.2 22.8 C6.8 2900 0.56 C131.5 25.2 C7.6 3000 0.58 C124.9 27.9 C7.9 adc reference the internal voltage reference can be confgured for two pin-selectable adc input ranges. tying the sense pin to v dd selects the default range; tying the sense pin to 1.5v selects a 3db lower range. an external reference can be used by applying its output directly or through a resistor divider to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. the sense pin is internally bypassed to ground with a 1f ceramic capacitor. applications information the lo input port is internally matched over a wide fre- quency range from 1.5ghz to 2.7ghz with input return loss typically better than 10db. no external matching network is needed for this frequency range. when the part is operated at a lower frequency, the input return loss can be improved with the matching network shown in figure 8. shunt capacitor c12 and series capacitor c13 can be selected for optimum input impedance matching at the desired frequency as illustrated in figure 6. for lower frequency operation, external matching component c13 can serve as the series dc blocking capacitor. figure 5. lo input interface figure 6. lo return loss vs frequency lo external matching network for low band and mid band c12 9004 f05 c13 lo quadrature generator and buffer amplifiers lo input h4 h3 ?30 ?25 ?20 ?15 ?10 ?5 0 100 1000 10000 frequency (mhz) return loss (db) 9004 f06 no matching elements 1.95ghz match (2.7nh + 1.5pf) 700mhz match (15pf + 6.8pf)
LTM9004 18 9004f enable interface the enable voltage necessary to turn on the mixer is 2v. to disable or turn off the mixer, this voltage should be below 1v. if this pin is not connected, the mixer is dis- abled. however, it is not recommended that the pin be left foating for normal operation. the amp1enable and amp2enable pins are cmos logic inputs with internal pull-up resistors. if the pin is driven low, the amplifer powers down with hi-z outputs. if the pin is left unconnected or driven high, the part is in normal active operation. some care should be taken to control leakage currents at this pin to prevent inadvertently putting it into shutdown. the turn-on and turn-off time between the shutdown and active states are typically less than 1s. sleep and nap modes the converter may be placed in shutdown or nap modes to conserve power. connecting adcshdnx to gnd results in normal operation. connecting adcshdnx to v dd and oe x to v dd results in sleep mode, which powers down all circuitry including the reference and the adc typically dissipates 1mw. when exiting sleep mode, it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting adcshdnx to v dd and oe x to gnd results in nap mode and the adc typically dissipates 30mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. channels i and q have independent adcshdn pins (adcshdni, adcshdnq.) i-channel is controlled by adcshdni and oei , and q-channel is controlled by adcshdnq and oeq . the nap, sleep and output enable modes of the two channels are completely independent, so it is possible to have one channel operating while the other channel is in nap or sleep mode. note that adcshdn has the opposite polarity as mixen - able, amp1enable and amp2enable. normal operation is achieved with a logic low level on the shdn pins and a high level disables the respective functions. it is not recommended to enable or shut down individual components separately. these pins are separated for test purposes. driving the adc clock inputs the clk inputs can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low-jitter squaring circuit before the clk pin (figure 7). applications information figure 7. sinusoidal single-ended clk driver clk 50 0.1f 0.1f 4.7f 1k 1k ferrite bead clean supply sinusoidal clock input 9004 f07 nc7svu04 LTM9004 the noise performance of the adc can depend on the clock signal quality as much as on the analog input. any noise present on the clk signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, such as when digitizing high input frequencies, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, flter the clk signal to reduce wideband noise and distortion products generated by the source. it is recommended that clki and clkq are shorted to- gether and driven by the same clock source. if a small time delay is desired between when the two channels sample the analog inputs, clki and clkq can be driven by two different signals. if this time delay exceeds 1ns, the performance of the part may degrade. clki and clkq should not be driven by asynchronous signals.
LTM9004 19 9004f clk 5pf-30pf etc1-1t 0.1f ferrite bead differential clock input 9004 f09 LTM9004 v dd 2 figure 8 and figure 9 show alternatives for converting a differential clock to the single-ended clk input. the use of a transformer provides no incremental contribution to phase noise. the lvds or pecl to cmos translators provide little degradation below 70mhz, but at 140mhz will degrade the snr compared to the transformer solution. the nature of the received signals also has a large bear - ing on how much snr degradation will be experienced. for high crest factor signals such as wcdma or ofdm, where the nominal power level must be at least 6db to 8db below full scale, the use of these translators will have a lesser impact. the transformer in the example may be terminated with the appropriate termination for the signaling in use. the use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. the center tap may be bypassed to ground through a capacitor close to the adc if the differential signals originate on a different plane. the use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10 to 20 series resistor to act as both a lowpass flter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for refections. maximum and minimum conversion rates the maximum conversion rate for the adc is 125msps. the lower limit of the sample rate is determined by the droop of the sample-and-hold circuits. the pipelined architecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specifed minimum operating frequency for the LTM9004 is 1msps. clock duty cycle stabilizer an optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. using the clock duty cycle stabilizer is recommended for most applications. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. applications information figure 8. clk driver using an lvds or pecl to cmos converter figure 9. lvds or pecl clk drive using a transformer clk 100 0.1f 4.7f ferrite bead clean supply 9004 f08 LTM9004
LTM9004 20 9004f for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. if the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. digital outputs table 3 shows the relationship between the analog input voltage, the digital data bits, and the overfow bit. note that of is high when an overfow or underfow has occurred on either channel i or channel q. table 3. output codes vs input voltage input of d13 C d0 (offset binary) d13 C d0 (2s complement) overvoltage 1 11 1111 1111 1111 01 1111 1111 1111 maximum 0 0 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1110 0 0 0 0 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 minimum 0 0 00 0000 0000 0001 00 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0000 undervoltage 1 00 0000 0000 0000 10 0000 0000 0000 digital output modes figure 10 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, iso- lated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 to external circuitry and may eliminate the need for external damp- ing resistors. as with all high speed/high resolution converters the digi - tal output loading can affect the performance. the digital outputs of the adc should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. for full speed operation, the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs. data format using the mode pin, the adc parallel digital output can be selected for offset binary or 2s complement format. note that mode controls both i and q channels. connecting mode to gnd or 1/3 v dd selects straight binary output format. connecting mode to 2/3 v dd or v dd selects 2s complement output format. an external resistive divider can be used to set the 1/3 v dd or 2/3 v dd logic values. table 4 shows the logic states for the mode pin. table 4. mode pin function mode pin output format clock duty cycle stabilizer 0 straight binary off 1/3v dd straight binary on 2/3v dd 2s complement on v dd 2s complement off overfow bit when of outputs a logic high the converter is either over - ranged or underranged on i-channel or q-channel. note that both channels share a common of pin. of is disabled when i-channel is in sleep or nap mode. applications information figure 10. digital output buffer LTM9004 9004 f10 ov dd v dd v dd 0.1f 43 typical data output ognd ov dd 0.5v to 3.6v predriver logic data from latch oe
LTM9004 21 9004f output clock the adc has a delayed version of the clkq input available as a digital output, clkout. the falling edge of the clkout pin can be used to latch the digital output data. clkout is disabled when channel q is in sleep or nap mode. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same supply that powers the logic being driven. for example, if the converter drives a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to the v dd of the part. ognd can be powered with any volt- age from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe . oe high disables all data outputs including of. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. the output hi-z state is intended for use during long periods of inactivity. channels i and q have independent output enable pins ( oei , oeq .) digital output multiplexer the digital outputs of the adc can be multiplexed onto a single data bus. the mux pin is a digital input that swaps the two data busses. if mux is high, i-channel comes out on di0 to di13; q-channel comes out on dq0 to dq13. if mux is low, the output busses are swapped and i-channel comes out on dq0 to dq13; q-channel comes out on di0 to di13. to multiplex both channels onto a single output bus, connect mux, clki and clkq together (see the tim - ing diagrams for the multiplexed mode.) the multiplexed data is available on either data bus C the unused data bus can be disabled with its oe pin. applications information design example C umts uplink fdd system the LTM9004 can be used with an rf front end to build a complete umts band uplink receiver. an rf front end will consist of a diplexer, along with one or more lnas and bandpass flters. here is an example of typical performance for such a frontend: rx frequency range: 1920 to 1980 mhz rf gain: 15db maximum agc range: 20db noise fgure: 1.6db iip2: 50dbm iip3: 0dbm p1db: C9.5dbm rejection at 20mhz: 2db rejection at tx band: 95db minimum performance of the receiver is detailed in the 3gpp ts25.104 v7.4.0 specifcation. we will use the medium area basestation in operating band i for this example. sensitivity is a primary consideration for the receiver; the requirement is ?C111dbm, for an input snr of C19.8db/5mhz. that means the effective noise foor at the receiver input must be ?C158.2dbm/hz. given the effective noise contribution of the rf frontend, the maxi - mum allowable noise due to the LTM9004 must then be C142.2dbm/hz. typical input noise for the LTM9004 is C148.3dbm/hz, which translates to a calculated system sensitivity of C116.7dbm. typically such a receiver enjoys the benefts of some dsp fltering of the digitized signal after the adc. in this case assume the dsp flter is a 64 tap rrc lowpass with alpha equal to 0.22. to operate in the presence of co-channel in - terfering signals, the receiver must have suffcient dynamic range at maximum sensitivity. the umts specifcation calls for a maximum co-channel interferer of C73dbm. note the input level for C1dbfs within the if passband of the LTM9004 is C15.1dbm for a modulated signal with a 10db crest factor. the tone interferer amounts to a peak digitized signal level of C42.6dbfs.
LTM9004 22 9004f applications information with the rf agc set for minimum gain, the receiver must be able to demodulate the largest anticipated desired signal from the handset. this requirement ultimately sets the maximum signal the LTM9004 must accommodate at or below C1dbfs. assuming a handset average power of +28dbm, the minimum path loss called out in the specif - cation is 53db. the maximum signal level is then C25dbm at the receiver input, or C30dbm at the LTM9004 input. this is equivalent to C14.6dbfs peak. there are several blocker signals detailed in the umts system specifcation. the sensitivity may degrade to no more than C105dbm in the presence of these signals. the frst of these is an adjacent channel 5mhz away, at a level of C42dbm. this amounts to a peak digitized signal level of C11.6dbfs. the resulting sensitivity is then C112.8dbm. the receiver must also contend with a C35dbm interfer - ing channel 10mhz away. the rf frontend will offer no rejection of this channel, so it amounts to C6.6dbfs peak, and the resulting sensitivity is C109.2dbm. out of band blockers must also be accommodated, but these are at the same level as the inband blockers which have already been addressed. in all of these cases, the typical input level for C1dbfs of the LTM9004 is well above the maximum anticipated signal levels. note that the crest factor for the modulated channels will be on the order of 10db to 12db, so the largest of these will reach a peak power of approximately C6.5dbfs at the module output. the largest blocking signal is the C15dbm cw tone 20mhz beyond the receive band edges. the rf frontend will offer 37db rejection of this tone, so it will appear at the input of the LTM9004 at C32dbm. here again, a signal at this level must not desensitize the baseband module. the equivalent digitized level is only C41.6dbfs peak, so there is no effect upon sensitivity. another source of undesired signal power is leakage from the transmitter. since this is an fdd application, the re - ceiver described herein will be coupled with a transmitter operating simultaneously. the transmitter output level is assumed to be +38dbm, with a transmit to receive isola - tion of 95db. leakage appearing at the LTM9004 input is then C42dbm, offset from the receive signal by at least 130mhz. the equivalent digitized level is only C76.6dbfs peak, so there is no desensitization. one challenge of direct conversion architectures is 2nd order linearity. insuffcient 2nd order linearity will allow any signal, wanted or unwanted, to create dc offset or pseudo-random noise at baseband. the blocking signals detailed above will then degrade sensitivity if this pseudo- random noise approaches the noise level of the receiver. the system specifcation allows for sensitivity degrada - tion in the presence of these blockers in each case. per the system specifcation, the C35dbm blocking channel may degrade sensitivity to C105dbm. this is equivalent to increasing the effective input noise of the receiver to C148.2dbm/hz. the 2nd order distortion produced by the LTM9004 input is about 18db below this level, and the resulting predicted sensitivity is C116.6dbm. the C15dbm cw blocker will also give rise to a 2nd order product; in this case the product is a dc offset. dc offset is undesirable, as it reduces the maximum signal the a/d converter can process. the one sure way to alleviate the effects of dc offset is to ensure the 2nd order linearity of the baseband module is high enough. the predicted dc offset due to this signal is <1mv at the adc input. note that the transmitter leakage is not included in the system specifcation, so the sensitivity degradation due to this signal must be held to a minimum. the 2nd order distortion generated in the LTM9004 is such that the loss of sensitivity will be <0.1db. there is only one requirement for 3rd order linearity in the specifcation. in the presence of two interferers, the sensitivity must not degrade below C105dbm. the inter - ferers are a cw tone and a wcdma channel at C44dbm each. these will appear at the LTM9004 input at C29dbm each. their frequencies are such that they are 10mhz and 20mhz away from the desired channel, so the 3rd order intermodulation product falls at baseband. here again, this product appears as pseudo-random noise and thus will reduce signal to noise ratio. for a sensitivity of C105dbm, the allowable 3rd order distortion referred to the receiver input is then C148.2dbm/hz. the 3rd order distortion produced in the LTM9004 is about 23db below this level, and the predicted sensitivity degradation is <0.1db.
LTM9004 23 9004f supply sequencing the v cc pins provide the supply to the mixer and all ampli - fers and the v dd pins provide the supply to the adc. the mixer, amplifers and adc are separate integrated circuits within the LTM9004; however, there are no supply sequenc - ing considerations beyond standard practice. grounding and bypassing the LTM9004 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the LTM9004 has been optimized for a fowthrough layout so that the interaction between inputs and digital outputs is minimized. a continuous row of ground pads facilitates a layout that ensures that digital and analog signal lines are separated as much as possible. the LTM9004 is internally bypassed with the adc (v dd ), mixer and amplifer (v cc ) supplies returning to a common ground (gnd). the digital output supply (ov dd ) is returned to ognd. a 0.1f bypass capacitor should be placed at each of the two ov dd pins. additional bypass capacitance is optional and may be required if power supply noise is signifcant. heat transfer most of the heat generated by the LTM9004 is transferred through the bottom-side ground pads. for good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of suffcient area with as many vias as possible. recommended layout the high integration of the LTM9004 makes the pcb board layout simple. however, to optimize its electrical and thermal performance, some layout considerations are still necessary. ? use large pcb copper areas for ground. this helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. common ground (gnd) and output ground (ognd) are electrically isolated on the LTM9004, but can be connected on the pcb underneath the part to provide a common return path. ? use multiple ground vias. using as many vias as pos - sible helps to improve the thermal performance of the board and creates necessary barriers separating analog and digital traces on the board at high frequencies. ? separate analog and digital traces as much as pos - sible, using vias to create high frequency barriers. this will reduce digital feedback that can reduce the signal-to-noise ratio (snr) and dynamic range of the LTM9004. figures 11 through 14 give a good example of the recom - mended layout. the quality of the paste print is an important factor in producing high yield assemblies. it is recommended to use a type 3 or 4 printing no-clean solder paste. the solder stencil design should follow the guidelines outlined in application note 100. the LTM9004 employs gold-fnished pads for use with pb-based or tin-based solder paste. it is inherently pb-free and complies with the jedec (e4) standard. the materi - als declaration is available online at http://www.linear. com/leadfree/mat_dec.jsp. applications information
LTM9004 24 9004f applications information figure 11. layer 1 figure 12. layer 2
LTM9004 25 9004f applications information figure 13. layer 3
LTM9004 26 9004f applications information figure 14. layer 4
LTM9004 27 9004f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description lga package 204-lead (22mm 15mm 2.82mm) (reference ltc dwg # 05-08-1822 rev ?) 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 l k j h g f e d c b m a l k j h g f e d c b m a notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222 5. primary datum -z- is seating plane 6. t he total number of pads: 204 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.15 0.10 0.05 2.670 ? 2.970 detail b detail b substrate mold cap 0.27 ? 0.37 2.40 ? 2.60 bbb z z 22 bsc package top view 15 bsc 4 pad 1 corner x y aaa z aaa z 20.32 bsc 1.27 bsc 0.12 ? 0.28 package bottom view 3 pads see notes detail a 0.635 0.025 sq. 204x s y x eee suggested pcb layout top view 0.0000 1.2700 1.2700 2.5400 2.5400 3.8100 3.8100 5.0800 5.0800 6.3500 6.3500 7.6200 8.8900 10.1600 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 7.6200 8.8900 10.1600 lga 204 0108 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? ?(0.635) pad 1 detail a 13.97 bsc
LTM9004 28 9004f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2011 lt 0211 ? printed in usa related parts part number description comments ltc2295 dual 14-bit, 10msps adc 120mw, 74.4db snr, 9mm x 9mm qfn ltc2296 dual 14-bit, 25msps adc 150mw, 74db snr, 9mm x 9mm qfn ltc2297 dual 14-bit, 40msps adc 240mw, 74db snr, 9mm x 9mm qfn ltc2298 dual 14-bit, 65msps adc 410mw, 74db snr, 9mm x 9mm qfn ltc2299 dual 14-bit, 80msps adc 445mw, 73db snr, 9mm x 9mm qfn ltc2284 dual 14-bit, 105msps adc 540mw, 72.4db snr, 88db sfdr, 64-pin qfn ltc2285 dual 14-bit, 125msps adc 790mw, 72.4db snr, 88db sfdr, 64-pin qfn lt5575 800mhz to 2.7ghz high linearity direct conversion quadrature demodulator 60dbm iip2 at 1.9ghz, nf = 12.7db, low dc offsets ltc6404-1/ ltc6404-2 600mhz, low noise, ac precision fully differential input/output amplifer/driver 3v or 5v, 1.5nv/ hz , very low distortion C92dbc at 10mhz ltc6406 3ghz low noise, rail-to-rail input differential adc driver low noise: 1.6nv/ hz , low power: 18a ltm9001 16-bit if/baseband receiver subsystem integrated 16-bit, 130msps adc, passive filter and fixed gain differential amplifer, 11.25mm 11.25mm lga package ltm9002 14-bit dual-channel if/baseband receiver subsystem integrated, dual 14-bit 125msps adcs, passive filters and fixed gain differential amplifers, up to 300mhz if range, 15mm 11.25mm lga package ltm9005 14-bit, if-sampling receiver subsystem integrated 14-bit, 125msps adc, saw filter, two gain stages with 20db variable gain control and rf mixer, 22mm 15mm lga package typical application v cc1 = 5v 9004 ta02 0 90 lo i + _adj LTM9004 i ? _adj q + _adj q ? _adj sdi sck sdo 0.1f ltc2634-12 (or ltc2654-16) rf ref 0.1f v cc = 5v cs/ld

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